1. Field of the Invention
The present invention relates generally to chip-on-chip integrated circuit (IC) packages. More particularly, the invention relates to chip-on-chip IC packages that are assembled and mounted onto a substrate having other components that are coupled through the substrate with the chip-on-chip IC package.
2. Description of the Related Art
In the field of integrated circuits, chip-on-chip packages are implemented within various electronic assemblies. The prominence of chip-on-chip packages is due, in part, to the relatively high degree of functionality provided by the chip-on-chip package. That is, two highly interdependent dies may be stacked together so that each die may quickly access information from the other die. For example, an application specific integrated circuit (ASIC) may require access to a dedicated analog-to-digital (A/D) converter. Thus, the ASIC and A/D converter may be stacked and packaged together such that the A/D converter's input and output (I/O) pads are directly coupled to the ASIC's I/O pads. This stacked arrangement allows the ASIC to quickly use the A/D converter's capabilities and convert analog signals to digital signals while reducing some of the problems associated with long interconnect wires between nonstacked devices, such as signal interference and degradation.
Additionally, conventional chip-on-chip packages typically occupy a relatively small footprint within the completed electronic assembly. That is, conventional chip-on-chip packages take up less surface area on the substrate than two separately packaged dies that are coupled together. This feature represents a significant advance towards the continuing goal of miniaturization of electronic assemblies.
FIG. 1 is a side view of a conventional chip-on-chip package 100. As shown, the chip-on-chip package 100 typically includes a first die 104, a second die 102, a substrate 114, a first plurality of bonding wires 108 that couple the first die 104 to the substrate 114, and a second plurality of bonding wires 106a and 106b that couple the first die 104 to the second die 102. A first die attach layer 112 is typically configured to attach the first die 104 to the substrate 114, and a second die attach layer 110 is configured to attach the second die 102 to the first die 104. Typically, the first die 104 has a nonactive portion (not shown) for mounting the second die 102 thereon.
The first plurality of bonding wires 108a and 108b couple conductive pads (not shown) of the first die 104 to conductive pads or traces (not shown) of the substrate 114, and the second plurality of bonding wires 106 couple conductive pads (not shown) of the second die 102 to conductive pads (not shown) of the first die 104.
Chip-on-chip packages are constructed and packaged using conventional packaging and assembly techniques. Initially, the first and second die are fabricated using conventional semiconductor processes. The first and second die will each include a plurality of conductive pads disposed on one surface. The first die 104 is then attached to the substrate 114 using the first die attach layer 112. The second die 102 is then attached to the first die 104 using the second die attach layer 110. Conductive pads of the first die 104 are then coupled to the substrate 114 using conventional wire bonding techniques. Likewise, conductive pads of the second die 102 are then coupled to conductive pads of the first die 104 using conventional wire bonding techniques. After the dies are coupled together and to the substrate, an encapsulation material 116 is then added to protect the bonding wires and dies from mechanical and electrical damage.
Although conventional chip-on-chip packages provide a means for reducing overall size of electronic assemblies, there are several disadvantages associated with conventional chip-on-chip packages. For example, bonding wires of conventionally assembled chip-on-chip packages have an associated conductance and capacitance that may be significant and may result in a reduction of reliability in certain high-speed applications. That is, wire bond interconnections provide limited electrical performance compared to several other interconnect types, such as flip chip interconnects. Additionally, bonding wires are associated with a decrease in the overall reliability of the chip-on-chip package. During the encapsulation process, the bonding wires may be displaced and result in an increase in the number of shorts within the chip-on-chip package. By way of another example, the assembly process for conventional chip-on-chip packages is relatively complex and expensive. By way of another example, the delicate bonding wires of conventional chip-on-chip packages require encapsulation material to protect them from stresses, and, thus, the overall size of the conventional chip-on-chip package is increased accordingly by the amount of encapsulation material that is used. Additionally, conventional chip-on-chip packages using wire bond processes have limited product throughput that is dependent on throughput of the underlying wire bond and mold processes.
In light of the above disadvantages of conventional chip-on-chip packages, there is still a need for an improved chip-on-chip package that has a relatively small overall package size and high reliability. Additionally, there is a need for a simplified method for making such an improved package and mounting such a package onto a substrate.